Sub-10nm Carbon Nanotube Transistor

Scientists at IBM T. J. Watson Research Center demonstrated the first sub-10nm CNT transistor, which is shown to outperform the best competing silicon devices with more than four times the diameter-normalized current density (2.14 mA/μm) at a low operating voltage of 0.5V. 

"We've made nanotube transistors at aggressively scaled dimensions, and shown they are tremendously better than the best silicon devices" said Aaron Franklin, main author of the paper.

To test how the size of a nanotube transistor affected its performance, Franklin's group made multiple transistors of different sizes along a single nanotube. This enabled them to control for any variations that might occur from nanotube to nanotube. First, they had to lay down a very thin layer of insulating material for the nanotube to sit on. And they developed a two-step process for adding electrical gates to the nanotube without damaging it. These techniques are by no means ready for manufacturing, but they enabled the IBM group to make the first nanotube devices smaller than 10 nanometers to test in the lab. The work is described online in the journal Nano Letters. 
Several major engineering problems remain, says Franklin. First, researchers have to come up with better methods for making pure batches of semiconducting nanotubes—metallic tubes in the mix will short out integrated circuits. Second, they must come up with a way to place large numbers of nanotubes on a surface with perfect alignment.

The superior low-voltage performance of this CNT transistor proves the viability of nanotubes for consideration in future aggressively scaled transistor technologies.

Sub-10 nm Carbon Nanotube Transistor

Aaron D. Franklin, Mathieu Luisier, Shu-Jen Han, George Tulevski, Chris M. Breslin, Lynne Gignac, Mark S. Lundstrom, and Wilfried Haensch

Nano Letters 2012 12 (2), 758-762

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